Interface circuit for an integrated injection logic circuit

ABSTRACT

An interface circuit for an integrated injection logic circuit comprises a current mirror circuit having its input current value set by a first resistor and its input controlled by an output signal of the integrated injection logic circuit, a second resistor connected to a current path at the output side of the current mirror circuit, and output means connected to the current output terminal of the current mirror circuit.

BACKGROUND OF THE INVENTION

This invention relates to an interface circuit for an integrated injection logic circuit as used in an interface between the integrated injection logic circuit and the other circuit.

A fundamental circuit of the integrated injection logic circuit (I² L circuit) comprises, as shown in FIG. 1, a PNP transistor Q_(I) as an injector and an output NPN transistor Q₀ having at least one open collector. Since a greater load cannot be driven with one transistor Q₀, an interface circuit is required for the I² L circuit to drive the other circuit, for example, a TTL circuit.

FIGS. 2 and 3 each show a conventional interface circuit as used in an interface circuit between an I² L circuit and a TTL circuit. The interface circuit as shown in FIG. 2 comprises three NPN transistors Q₁ to Q₃, three resistors R₁ to R₃ and one diode D₁. An output of an I² L inverting gate G as configured in FIG. 1 is applied to the base of the NPN transistor Q₁. The interface circuit as shown in FIG. 3 comprises two PNP transistors Q₄, Q₅, two NPN transistors Q₆, Q₇ and seven resistors R₄ to R₁₀. An output of an I² L inverting gate G as configured in FIG. 1 is applied through the resistor R₅ to the base of the PNP transistor Q₄. In the conventional interface circuit it is not possible to obtain an arbitrary output voltage and there is a disadvantage that high and low level output voltages are fixed to certain levels. In the interface circuit of FIG. 2, for example, a high level output voltage is V_(CC) -2V_(F) and a low level output voltage is V_(CE) (sat) (Q₃). In the interface circuit as shown in FIG. 3 the high level output voltage is V_(CC) -V_(CE) (sat)(Q₅)-V_(BE) (Q₇) and the low level output voltage is zero (ground potential).

SUMMARY OF THE INVENTION

It is accordingly an object of this invention to provide an interface circuit for an integrated injection logic circuit which can freely set the value of an output voltage.

According to this invention there is provided an interface circuit for an integrated injection logic circuit comprising a first resistor, a current mirror circuit having its input current value set by a first resistor and having its input controlled by an output signal of the integrated injection logic circuit, a second resistor inserted in an electric current path at the output side of the current mirror circuit, and an output means connected to the output terminal of the current mirror circuit.

According to another embodiment of this invention there is provided an interface circuit for an integrated injection logic circuit which comprises a first resistor, a first current mirror circuit having its input current value set by the first resistor and having its input controlled by an output signal of the integrated injection logic circuit, a second current mirror circuit connected to receive an input current set by a second resistor and having its current output terminal connected at a common junction to a current output terminal of said first current mirror circuit, a third resistor connected to a common current path at the output side of the first and second current mirror circuits, and input means connected to the common current path of the first and second current mirror circuits.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a fundamental circuit of an I² L circuit;

FIG. 2 is a conventional interface circuit as used in an interface between an I² L circuit and a TTL circuit;

FIG. 3 is a conventional interface circuit as used in an interface between an I² L circuit and a TTL circuit;

FIG. 4 is an interface circuit for an integrated injection logic circuit according to one embodiment of this invention; and

FIGS. 5 to 9 each show an interface circuit for an integrated injection logic circuit according to another embodiment of this invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 4 shows an interface circuit for an integrated injection logic circuit according to one embodiment of this invention. The FIG. 4 circuit comprises two current mirror circuits M₁, M₂, an NPN transistor Q₁₅ and four resistors R₁₁ to R₁₄. The current mirror circuit M₁ comprises two NPN transistors Q₁₁, Q₁₂ having their bases connected in common and their emitter areas equal to each other. The emitters of the NPN transistors Q₁₁, Q₁₂ are each connected to ground and the collector-to-base path of the NPN transistor Q₁₁ is short-circuited. Likewise, the other current mirror circuit M₂ comprises two NPN transistors Q₁₃, Q₁₄ having their bases connected in common and their emitter areas equal to each other. The emitters of the NPN transistors Q₁₃, Q₁₄ are grounded and a collector-to-base path of the NPN transistor Q₁₄ is short-circuited. To a common junction of the bases of the NPN transistors Q₁₁, Q₁₂ in the current mirror circuit M₁ is connected an output terminal of an I² L inverting gate G at an output stage of the I² L circuit. A resistor R₁₁ is connected between the collector of the NPN transistor Q₁₁ at the input side of the current mirror circuit M₁ and the positive terminal of a power source V_(CC) to set an input current value I₁ of the current mirror circuit M₁. Likewise, a resistor R₁₂ is connected between the collector of the NPN transistor Q₁₄ at the input side of the other current mirror circuit M₂ and the positive terminal of the power source V_(CC) to set an input current value I₂ of the current mirror circuit M₂. The collectors of the NPN transistors Q₁₂, Q₁₃ at the output side of both the current mirror circuits M₁, M₂ are connected to each other and a resistor R₁₃ is connected between a junction P of the collectors of the transistors Q₁₂, Q₁₃ and the positive terminal of the power source V_(CC). The NPN transistor Q₁₅ and emitter resistor R₁₄ of the transistor Q₁₅ constitutes an emitter follower output circuit and the base of the NPN transistor Q₁₅ in the emitter follower output circuit is connected to the junction point P. An output terminal Out is connected to the emitter of the NPN transistor Q₁₅ and also to the input terminal of the other circuit such as a TTL circuit.

The operation of the interface circuit will be explained below.

With the I² L inverting gate G ON i.e. the NPN transistor Q₀ of FIG. 1 ON, an electric current I₁ through the resistor R₁₁ flows into the I² L inverting gate G, causing the NPN transistors Q₁₁, Q₁₂ to be cut off. As a result, the current mirror circuit M₁ is not operated. Since an electric current I₂ set by the resistor R₁₂ flows into the input side of the current mirror circuit M₂, an electric current I₂ of the same value also flows at the output side of the current mirror M₂. That is, the electric current I₂ flows through the resistor R₁₃. With the base-to-emitter voltage of the NPN transistor Q₁₅ represented by V_(BE) (Q₁₅), an output voltage V_(O) on the output terminal Out is given by the following equation:

    V.sub.O =V.sub.CC -I.sub.2 ·R.sub.13 -V.sub.BE (Q.sub.15) (1)

That is, the output voltage V_(O) is equal to value by subtracting a voltage drop I₂ ·R₁₃ through the resistor R₁₃ and base-to-emitter voltage V_(BE) (Q₁₅) of the NPN transistor Q₁₅ from the power source voltage V_(CC). At this time, the value of the output voltage V_(O) corresponds to a value at the high level output time.

With the I² L inverting gate G OFF, the electric current I₁ through the resistor R₁₁ flows through the current mirror circuit M₁ and thus flows through the NPN transistor Q₁₂ at the output side of the current mirror circuit M₁. As a result, an electric current corresponding to a sum of I₁ and I₂ flows through the resistor R₁₃ and at this time the output voltage V_(O) on the output terminal Out can be given by:

    V.sub.O =V.sub.CC -(I.sub.1 +I.sub.2)·R.sub.13 -V.sub.BE (Q.sub.15)                                                (2)

In this case, a voltage drop through the resistor R₁₃ becomes greater than the counterpart in the equation (1) and at this time a value of the output voltage V_(O) corresponds to a value at the low level output time.

Here, ##EQU1## with V_(OL) and V_(OH) representing the output voltage V_(O) at the low level time and output voltage V_(O) at the high level output voltage V_(O), respectively, the equations (1) and (2) can be rewritten as follows: ##EQU2## where V_(BE) (Q₁₁): the base-to-emitter voltage of the NPN transistor Q₁₁

V_(BE) (Q₁₄): the base-to-emitter voltage of the NPN transistor Q₁₄

As evident from the equations (5) and (6) the output voltages at the high and low level output times can be freely set by a ratio of the resistances of the resistors R₁₁, R₁₂ and R₁₃. Thus, the output voltage can be adjusted with high accuracy in obtaining an integrated circuit.

FIG. 5 shows an interface circuit according to another embodiment of this invention, in which two current mirror circuits M₁, M₂ are provided, one being constituted of two PNP transistors Q₂₁, Q₂₂ and the other being constituted of two PNP transistors Q₂₃, Q₂₄. In this case, an output voltage V_(O) becomes equal to a value as obtained by subtracting a basse-to-emitter voltage V_(BE) (Q₁₅) of an NPN transistor from a voltage drop through a resistor R₁₃. With an I² L inverting gate G ON the output voltage V_(O) becomes a high level V_(OH) and with the I² L inverting G OFF the output voltage V_(O) becomes a low level V_(OL). The values of V_(OH) and V_(OL) are given by: ##EQU3## where V_(BE) (Q₂₁): the base-to-emitter voltage of the PNP transistor Q₂₁

V_(BE) (Q₂₄): the base-to-emitter voltage of the PNP transistor Q₂₄

Even in this circuit, the values of the output voltages V_(OH), V_(OL) can be freely set by a ratio of the resistances of the resistors R₁₁, R₁₂ and R₁₃.

An interface circuit as shown in FIG. 6 corresponds to a circuit as obtained by eliminating a current mirror circuit M₂ and resistor R₁₂ from the FIG. 4 circuit. In this circuit, with an I² L inverting gate G ON an output voltage V_(OH) at the high level time is fixed at a value V_(CC) -V_(BE) (Q₁₅). With the I² L inverting gate G OFF the output voltage V_(OL) at the low level time becomes a value V_(CC) -I₁ ·R₁₃ -V_(BE) (Q₁₅). In this circuit, only the output voltage V_(OL) at the low level time can be freely varied by setting a ratio of the resistances of resistors R₁₁, R₁₃.

FIG. 7 shows an interface circuit in which the current mirror circuit M₁ of FIG. 6 is replaced by a current mirror circuit comprised of two PNP transistors Q₂₁, Q₂₂. In this circuit, with the I² L inverting gate G OFF an output voltage V_(OL) at the lower level time is fixed at a low level i.e. at a ground level. With the I² L inverting gate G ON, the output voltage V_(OH) at a high level time becomes a value I₁ ·R₁₃ -V_(BE) (Q₁₅). In this circuit, only an output voltage V_(OH) at the high level time can be freely varied by setting a ratio of the resistances of resistors R₁₁, R₁₃.

This invention is not restricted to the above-mentioned embodiments. Although this invention has been explained in connection with, for example, the case where two transistors of each of the current mirror circuits M₁, M₂ have the equal emitter areas, a greater or a smaller output current may be taken from the output side of the circuit with the emitter areas of the two transistors set at a predetermined ratio.

Instead of setting the ratio of the emitter areas of the pair of transistors constituting the current mirror circuit, a resistor R₁₅ may be connected to the emitter circuit of one of a pair of transistors in the current mirror circuit as shown in FIGS. 8 and 9 and, by so doing, a greater or a smaller output current may be taken from an output side. Since in the circuit as shown in FIGS. 8 and 9 the resistor R₁₅ is connected to the emitter circuit of the NPN transistor Q₁₁ at the input side of the current mirror circuit M₁, a greater output current is taken from the output side. 

What is claimed is:
 1. An interface circuit for use with an integrated injection logic circuit, comprising:first and second power source terminals; first and second resistors each having a first end connected to said first power source terminal; a current mirror circuit connected to said integrated injection logic circuit and having an input current path and an output current path, said input and output current mirror paths being respectively connected between said second power source terminal and the respective second ends of said first and second resistors, and whereby the input current value of said current mirror circuit is set by said first resistor and the input of said current mirror circuit is controlled by the output signal of said integrated injection logic circuit; and output means connected to said second end of said second resistor.
 2. The interface circuit for an integrated injection logic circuit according to claim 1, in which said output means includes an emitter follower circuit comprising a transistor having its base connected to the second terminal of said second resistor and a resistor connected between the emitter and the second power source terminal.
 3. The interface circuit according to claim 1, wherein said current mirror circuit comprises a first transistor, which has a collector and a base both connected to said second end of said first resistor and an emitter connected to said second power source terminal, and a second transistor, which has a collector connected to said second end of said second resistor, a base connected to said base of said first transistor and an emitter connected to said second power source terminal.
 4. The interface circuit according to claim 3, wherein an emitter circuit of at least one of said first and second transistors includes a third resistor.
 5. An interface circuit for an integrated injection logic circuit, comprising:first and second power source terminals; first, second and third resistors each having a first end connected to said first power source terminal; a first current mirror circuit connected to said integrated injection logic circuit and having an input current path and an output current path, said input and output current mirror paths being respectively connected between said second power source terminal and the respective second ends of said first and third resistors, whereby the input current value of said first current mirror circuit is set by said first resistor and the input of said first current mirror circuit is controlled by the output signal of said integrated injection logic circuit; a second current mirror circuit having an input current path and an output current path, said input and output current mirror paths being respectively connected between said second power source terminal and the respective second ends of said second and third resistors, and whereby the input current value of said second current mirror circuit is set by said second resistor; and output means connected to said second end of said third resistor.
 6. The interface circuit for an integrated injection logic circuit according to claim 5, in which said output means includes an emitter follower circuit comprising a transistor having its base connected to the second terminal of said third resistor and an emitter resistor.
 7. The interface circuit according to claim 5, wherein said first current mirror circuit comprises a first transistor, which has a collector and a base both connected to said second end of said first resistor and an emitter connected to said second power source terminal, and a second transistor, which has a collector connected to said second end of said third resistor, a base connected to said base of said first transistor and an emitter connected to said second power source terminal, and wherein said second current mirror circuit comprises a third transistor, which has a collector and a base both connected to said second end of said second resistor and an emitter connected to said second power source terminal, and a fourth transistor, which has a collector connected to said second end of said third resistor, a base connected to said base of said third transistor and an emitter connected to said second power source terminal.
 8. The interface circuit according to claim 7, wherein an emitter circuit of at least one of said first to fourth transistors includes a fourth resistor. 